Include .qsys Qsys systems to VHDL Quartus project

Hi Mohamed,

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I would like to use option 1 (include .qsys file into the project) and have Quartus build it to be able to include it from a VHDL file. Right now, it seems to generate the Qsys system top IP in Verilog no matter what and there is no option to ask for VHDL.

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I haven't found any way to control the build via including .qsys directly, which is why I went with Tcl scripting.

Practically though, why do you care if its VHDL? So long as the design synthesizes, you shouldn't really need to care.

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I use .qip file generated by Qsys at the moment and asks Qsys to generate the top IP in VHDL. However, I would like to move to .qsys file to be able to directly go into the system in Qsys from Quartus and for ease of use. My goal here is to avoid any manual steps such as generating the Qsys system from Qsys (needed right now) or modifying a TCL script.

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There are no manual steps with the Tcl script. The script automates everything.

In the case of the DDR controller, it also automates the application of the DDR pin constraints file generated by the IP core via a post-flow script. None of the Altera examples do this :)

Cheers,

Dave