Include .qsys Qsys systems to VHDL Quartus project

Dave,

I had a look at the project but if I get it correctly, it is not what I would like to do.

I would like to use option 1 (include .qsys file into the project) and have Quartus build it to be able to include it from a VHDL file. Right now, it seems to generate the Qsys system top IP in Verilog no matter what and there is no option to ask for VHDL.

I use .qip file generated by Qsys at the moment and asks Qsys to generate the top IP in VHDL. However, I would like to move to .qsys file to be able to directly go into the system in Qsys from Quartus and for ease of use. My goal here is to avoid any manual steps such as generating the Qsys system from Qsys (needed right now) or modifying a TCL script.

Regards,

Mohamed