--- Quote Start ---
HI, I have a question what is# 1 in the command here. Is it just a comment. Sorry, im a newbie in verilog.
module simple_counter (
CLOCK_50,
counter_out
);
input CLOCK_50 ;
output counter_out;
reg counter_out;
always @ (posedge CLOCK_50) // on positive clock edge
begin
counter_out <=# 1 counter_out + 1;// increment counter
end
endmodule // end of module counter
module simple_counter (
CLOCK_50,
counter_out
);
input CLOCK_50 ;
output counter_out;
reg counter_out;
always @ (posedge CLOCK_50) // on positive clock edge
begin
counter_out <= #1 counter_out + 1;// increment counter
end
endmodule // end of module counter
--- Quote End ---
# 1 indicates that the output "counter_out" is delayed by 1 time unit after the rising edge of the clock. The units (ns, ps, etc.) are defined by a separate `timescale statement or the system verilog command "timeunit." At any rate, it's not shown in your code. I've come across many designers in my career who put a delay in every single line of their synthesizable code so it looks more realistic in the simulator. I do NOT recommend this, as this will affect the simulator speed. And quite frankly, it's a nuisance to type. In addition, these delays are ignored by synthesis tools, and many of them will print out a warning that the delay was ignored for every statement.
However, delays such as these are very useful and necessary in testbenches.
Robert
lead VHDL/Verilog trainer
www.digitaldesignconcepts.org (
http://www.digitaldesignconcepts.org)
Honored Contributor
