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Altera_Forum
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11 years ago

In verilog when the default case in a case statement is ignored by synthesis

I recently discovered that unless you specifically use the global assignment SAFE_STATE_MACHINE ON, the default case where the case statement is part of a state machine will be ignored. IE, not synth...
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Altera_Forum
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11 years ago

They do spell out quite clearly in the quartus documentation what the state encoding does, and how it is chosen, but also that you are free to chose your own encoding scheme.