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Altera_Forum
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11 years ago

In verilog when the default case in a case statement is ignored by synthesis

I recently discovered that unless you specifically use the global assignment SAFE_STATE_MACHINE ON, the default case where the case statement is part of a state machine will be ignored. IE, not synth...
Altera_Forum's avatar
Altera_Forum
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11 years ago

I think what may be happening is that the compiler knows that the non-default cases cover all possible values of the state variable. Therefore it knows the default case will never be reached and correctly optimizes it away.