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万江's avatar
万江
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7 years ago

In A10/C10 hard ip for PCIe, size of address pages can't be 128KB to 2MB

Hello, I'm testing PCIe on a C10 devkit by quartus 18.0pro. Application interface type = Avalon_MM(no DMA), Avalon_MM address width = 32bits. Under Avalon-MM settings tab, why size of address pag...
Nathan_R_Intel's avatar
Nathan_R_Intel
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7 years ago

Jiang,

Could you send me your design achieve (.qar) so, I can understand what you mean by TXS cannot be connected to main QSYS directly. Currently, from your description alone its vague.

Also when you changed your AVMM address width = 64 bi with PCIE address width of accessible PCIe memory space is 64 bits; it allows all 64 bits to be accessible.

Regards,

Nathan