Hie Jiang Wanli,
My apologies for responding after almost a month. I posted a reply on 1st July but seems like it did not get posted. My apologies on that.
I will retype my previous post
Yes, you are correct, the Address Translation Table is only available when Avalon-MM address width is 32 bits. Your testing is correct.
My previous note was misleading to mention that Address Translation Table is also available for 64 bits. As described in our user guide Section A.4.10, no address translation is available when using Avalon-MM address width = 64 bits.
Also I can confirm that only one address page is available when using AVMM address width = 64 bits.
Hence, thats the reason for your following observation:
"Under Avalon-MM settings tab, 'Number of address pages' and 'Size of address pages' appear, and 'Address width of accessible PCIe memory space' disappears"
So when using AVMM address width = 64
This is my response to the following questions:
Question for using AVMM address width = 32;
If I set Number of address pages = 16 and Size of address pages = 64KBytes(16 bits), from Component Instantiation \ Compilation Info \ Signals & Interfaces, I read the address width of 'txs interface' is 20bits. That is 64KB * 16 = 1MB.
On qsys side:
address[15:0] are passed through and become PCIe address[15:0]
address[19:16] select one from the 16 address translation table entries
address[31:20] are determined by Assign Base Addresses
On PCIe side:
address[15:0] are identical with qsys address[15:0]
address[31:16]/address[63:16] come from the selected address translation table entry, b[1:0] of which determine 32 or 64bits address
Response:
Your interpretation of the address translation table seems correct per my understanding.
Question for using AVMM address width = 64:
Now I guess, PCIe address[21:0] are identical with qsys address[21:0]
But how about PCIe address[31/63:22]? And how about the PCI address width, 32 or 64 bits? Something fixed or by address translation table entry #0?
Response:
When using Address width of accessible PCIe memory space = 22, the PCIE address width of accessible PCIe memory space is 22bits.
Yes,[21:0] is the PCIe address bits.
Hence, the remaining PCIe address [31/63:22] is not accessible. Your PCIe address width is 64 bits buts only 22 bits is accessible.
Its not fixed by any address translation table.
Regards,
Nathan
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