In A10/C10 hard ip for PCIe, size of address pages can't be 128KB to 2MB

Hi Nathan,

Thank you for your explanation

But according to my testing, I feel the Address Translation Table is available only when Avalon_MM address width = 32bits

---------------------------------------------------------------------

When Avalon_MM address width = 32 bits

Under Avalon-MM settings tab, 'Number of address pages' and 'Size of address pages' appear, and 'Address width of accessible PCIe memory space' disappears

If I set Number of address pages = 16 and Size of address pages = 64KBytes(16 bits), from Component Instantiation \ Compilation Info \ Signals & Interfaces, I read the address width of 'txs interface' is 20bits. That is 64KB * 16 = 1MB.

On qsys side:

address[15:0] are passed through and become PCIe address[15:0]

address[19:16] select one from the 16 address translation table entries

address[31:20] are determined by Assign Base Addresses

On PCIe side:

address[15:0] are identical with qsys address[15:0]

address[31:16]/address[63:16] come from the selected address translation table entry, b[1:0] of which determine 32 or 64bits address

---------------------------------------------------------------------

When Avalon_MM address width = 64bits

'Number of address pages' and 'Size of address pages' disappear, and 'Address width of accessible PCIe memory space' appears

If I set Address width of accessible PCIe memory space = 22, I read the address width of 'txs interface' is 22bits. Obviously no paging or only one page.

Now I guess, PCIe address[21:0] are identical with qsys address[21:0]

But how about PCIe address[31/63:22]? And how about the PCI address width, 32 or 64 bits? Something fixed or by address translation table entry #0?

Section A.4.10 is for 32 bit addressing only, and it said 'If you select 64-bit addressing the bridge does not perform address translation.'

Regards,

Jiang Wanli