In A10/C10 hard ip for PCIe, size of address pages can't be 128KB to 2MB

Wanli Jiang, My apologies for the delayed first response. I missed your case and will provide faster response moving forward. Please check my response to your question: Currently, due to address translation algorithm, some size of address pages cannot be set. The address translation replaces the MSB of AVMM address with value from a specific translation table. Only the LSB remains unchanged. Hence, that's why you cannot set to between 17-21 bits. Question: the way, if Avalon_MM address width = 64bits, and address width of accessible PCIe memory space = 20. When an avalon-mm to PCIe transaction occurs, what are higher 42 address bits on PCIe? All zeroes? Answer: Avalon address is interpreted as following for 64 bits: • Bits [31:24] select the TX slave module port from among other slaves connected to the same master by the system interconnect fabric. The decode is based on the base addresses assigned in Platform Designer. • Bits [23:20] select the address translation table entry. • Bits [63:20] of the address translation table entry become PCI Express address bits [63:20]. • Bits [19:0] are passed through and become PCI Express address bits [19:0]. More information related to AVMM to PCIe Address Translation is available in Section A.4.10 (Pg 174) of our user guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf Regards, Nathan