Forum Discussion
Import tcl-script to Quartus
After creating the list of modifications in the ECO file using Change Manager in Chip Planner, I exported the modifications as a tcl file.
But I can’t import this file into the project. After starting it through the TCL sripts built-in utility, an error appears on the command line:
<Error: ERROR: Unable to find Chip Planner netlist. Read the netlist by using the "read_netlist" command.>
Inside the tcl file, the read_netlist command is executed. And of course I am doing a full compilation of the project before this
16 Replies
- KhaiChein_Y_Intel
Regular Contributor
Hi,
May I know which edition and version of the software you are using? Could you provide a sample test case and steps to reproduce the error?
Thanks.
- wayne
New Contributor
Thanks for the answer. The problem was in environment variables for Windows. It was necessary to indicate the path for Quartus.
But now i have another problem. After applying ECO modifications the refitting of the project is carried out.
As a result, my LogicLock areas are ignored.
Is there any way to keep them in this situation?
- KhaiChein_Y_Intel
Regular Contributor
Hi,
I created a test case using the Pro Edition v19.3 and made the ECO changes using .tcl. The logic lock remains after applying the ECO. May I know which edition and version of the software you are using? Can you share the teat case you are using and the steps to reproduce the error?
Thanks.
- wayne
New Contributor
Hi,
the problem appears in case of a change in the structure of the adder. Each adder is placed in a specific LAB using LogicLock.
The first cell of each adder always has Operation Mode: Normal.
Subsequent cells have Operation Mode: Arithmetic.
The last cell in LAB again has Operation mode: Normal.
I need each adder to be connected via Cin / Cout carry chains and not through Combout / DataABCD.
As a result of the corrections in the Resource Property Editor, I delete the LEs that work in normal mode and connect each LAB through the carry chains.
But after executing "Check And Save netlist", fitter cannot route every adder in the specified LAB, but route them outside of LogicLock. In this case, the adders are routed vertically, not horizontally.
I guess the problem is not with LogicLock itself, but with the principles of the LE structure.
- KhaiChein_Y_Intel
Regular Contributor
Hi,
You may share the test case, steps and software version/edition, I can help to replicate here.
Thanks.
- wayne
New Contributor
Hi,
move_mod.tcl script inside the project.
The above problem starts when, after running the script, I start modifying the adder cells.
Version is Quartus Prime 15.1
- KhaiChein_Y_Intel
Regular Contributor
Hi,
Thanks for the attachment. Could you share the steps to reproduce the error? I tried to run the .tcl file but internal error occurred.
Thanks.
- wayne
New Contributor
Hi,
first I do a full compilation of the project in Quartus. Then close the quartus, execute the move_mod.tcl script using cmd.exe.
For this, I execute only one command "quartus_cdb -t move_mod.tcl".
- KhaiChein_Y_Intel
Regular Contributor
Hi,
I did the steps below:
- Compile the design in the Intel Quartus Prime software
- Close the software
- Execute the command: quartus_cdb -t move_mod.tcl
- Open the modules that are Logic Lock in Chip Planner
The modules are located within the logic lock area. See screenshot below.
Thanks.
- KhaiChein_Y_Intel
Regular Contributor