Forum Discussion

JNika's avatar
JNika
Icon for New Contributor rankNew Contributor
8 years ago

Import Package error System Verilog

Hello, I have a few packages that I have written like this: package A; -- -- endpackage package B; import A::* --- -- endpackage package C; import A::*; import B::*; endpackage In th...
dave_59's avatar
dave_59
Icon for New Contributor rankNew Contributor
8 years ago

It would help if you showed the places where TMP was declared and referenced. The import A::* by itself is not the problem. Most likely because you have declared TMP in both packages A and B and tried to reference it in C.