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JNika's avatar
JNika
Icon for New Contributor rankNew Contributor
7 years ago

Import Package error System Verilog

Hello, I have a few packages that I have written like this: package A; -- -- endpackage package B; import A::* --- -- endpackage package C; import A::*; import B::*; endpackage In th...
Vicky1's avatar
Vicky1
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

"Is this problem because I am importing A::* in both package A and package C?"

Yes, Please refer the below attached doc from Language reference manual(LRM) especially

"Table 26-1—Scoping rules for package importation" & Examples under the "26.6 Exporting imported names from packages"

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)