implementing vhdl I2C MUX in CPLD VHDL

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The I2C allows 2 masters and 8 slaves on the same bus. Do your really need to have a "mux"?

Anyway, if you really do need, you can do it by making the CPLD logic track the state of the I2C transaction, so it can known what direction to use for SDA.

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on each bus is going to be one master and one slave.

external hardwre configures whitch master is going to be connected to one of the 8 slaves.

how can the cpld track the state of the I2C transaction?

do you have ref design of guidelines ?

thanks