Implementing User-Defined "Wait For" time

That sounds very much correct if you were writing some C. But remember, this is VHDL (VHSIC Hardware Description Language), so you cannot just write a load of programming instructions and expect it to work. VHDL describes a logic circuit, not a load of instructions to execute in order (but it will also do that, but only in a simulation model - but dont think like this). You need to understand what circuit you're trying to create before writing any code. There is a lot of VHDL that is not synthesisable. I suggest you learn about the VHDL templates for synthesisable constructs (I suggest the Quartus manual, that contains all the templates you need). Or even a good textbook.