Implementing OpenCores SoC Design, lack an RS-232 port

Hello all,

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I was interested in using the STORM SoC (ARM-based processor, Wishbone bus) on an Altera Board - http://opencores.org/project,storm_soc

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I can fit the minimal STORM design in my board. I noticed that the design uses a UART for the bootloader console. My board does not have an RS-232 connector, however. I’ve only programmed a Nios processor with the JTAG UART before, so I’m not sure what direction to go.

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Would it be possible to use the USB blaster to provide this functionality? I noticed the JTAG to Avalon MM tutorial on the Altera Wiki - http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial#jtag-to-avalon-mm_tutorial_system_diagram .

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Since this design is platform agnostic, it isn’t a Qsys-based design. I see the JTAG to Avalon Master bridge as a component there – perhaps I could put an Avalon to Wishbone wrapper around that. Since I’m working outside of Qsys, I’m not sure that I have access to something like that. I don’t see it in the megafunction list. Would it be possible/sane to use the sld_virtual_jtag component to create a custom module that could act as a RS-232 input? Am I making life too difficult for myself by missing something obvious (it definitely would not be unprecedented)?

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Thanks,

Neophyte