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Altera_Forum
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17 years ago

Implementation and Timing of Reset Circuits

Most circuit designs employing FPGAs and ASICs are synchronous systems using a large number of flip-flops or registers. It is usually important that these synchronous elements are capable of startin...
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Altera_Forum
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16 years ago

I like the synchronized asynchronous reset described in this paper, however, I don't understand the need for the 2nd synchronizer register in the implementation shown in Figure 16. Since the input to the 1st synchronizer register is tied high, there shouldn't be any metastability issues with its output. Couldn't that be used directly instead of passing through another register? Thanks.