Implementation and Timing of Reset Circuits

Hi,

An interesting article, I guess you are the author.

I understand that in principle there are only two types of reset:

1)synchronous reset(gated with data) and

2)asynchronous reset(directly connected to port of flipflops)

It is also well-known that reset removal must be synchronised to its registers clock domain or else you will get problems especially as power-up differences of operation. I normally use a two stage synchroniser. The method explained in fig 16 of this article is interesting but I haven't tried it yet.

However, the article doesn't define clearly the LAB-wide synchronous reset and it implies at times that it is not gated but I assume it is also gated. I looked at the 766 pages of stratix ii handbook and there was only one occurence of synclr which was in a diagram same as your diagram.

There is no mention of chip-wide reset. I have never used it and I don't know it resets the firmware only or the configuration as well.

For power-up reset, I can use internal counter that counts up to a maximum and stops and then I can do my reset work on its count values which yields a synchronous reset that is connected to asynchronous ports.

As to external reset(synchronised or not), I believe in most cases it is waste of design since you can do a nice internal reset including power-up reset as mentioned above.

Thanks for the article.