CBrow36
New Contributor
New ContributorI'm wondering is whether there is a way to generate or not generate the jbc file based on an environment variable. Any ideas? I'd like to not create a jbc when I don't generate ALTPLL to speed simulation.
What started as a design workaround when I found that ALTPLL in Verilog was broken is also useful in simulation. I feed an external clock into the simulator and don't instantiate the PLL and it runs...
