I'M puzzled. why simulation wave is incorrect!

Hello,

the different results between the 2 byte and the 4 byte design are probably due to small timing differences from place and route. Quartus simulates an individual routed design unless you specify functional simulation.

Regarding timing analysis: What did you specify for input to clock relation? Probably nothing. The timing analysator won't expect that you intend to change input state exactly simultaneous with active clock transition. But the simulator should have reported the timing violation. You could simply switch the clock phase in *.vwf to remove the violation.

However, this consideration is somewhat unrealistic. In real life, I see two basic szenarios:

1. Input signals are synchronous to clock, cause they have a source somewhere in the same clock domain. Then their transition could be expected short behind active clock transition. And the timing analysator could watch them.

2. Input signals are asynchronous to clock and must be expected to change at any time. Then you are unable to get reliable results for input without either a handshake with signal source or a special coding of signals, e. g. gray code in case of a counter value.

Regards,

Frank