I'M puzzled. why simulation wave is incorrect!

Hi!

Thanks for your replay! Frank

But my timing analyzer report don't indicate any timing violation.

Timing Analyzer Sumary:

slack Required time Actual time From To

Worst-case tsu : 1.327ns 2.0ns 0.673ns in2[7] out2[7]~reg0

Worst-case tco : 3.047ns 9.0ns 5.593ns out2[7]~reg[0] out2[7]

Worst-case th : 0.485ns 1.0ns 0.515ns out1[0]~reg0

If I change the code as follow all the output results in the timming simmulation are correct. I just add two input and two output and set the same timing assingments which have been set in the front code.

module reg_four_chanel(clk,rst_n,in1,in2,in3,in4,out1,out2,out3,out4);

input clk,rst_n;

input[7:0] in1,in2,in3,in4;

output[7:0] out1,out2,out3,out4;

reg[7:0] out1,out2,out3,out4;

always@(posedge clk or negedge rst_n)

if(rst_n==1'b0)

begin

out1<=8'h00;

out2<=8'h00;

out3<=8'h00;

out4<=8'h00;

end

else

begin

out1<=in1;

out2<=in2;

out3<=in3;

out4<=in4;

end

endmodule

The same structure of code and same timming assingment, but the simmulation is different. I also think the timing constrain should be assingment but which particular

timing constrain should be assingment.