i'm a bit confused

firstly some answers:

I use the ALTERA Cyclone II Development Kit, which is populated by the EP2C35F672C6N and a Terasic TREX C1 Multimedia Development Kit, which is populated by the EP1C6Q240C8.

- the FPGA is powered up correctly

- the FPGA gets cofigured in the required way

- clock signals an other control signals are correct too

Source Code (Verilog)

--------------------------

// lsb

DFF A1(.d((~q3 && ~q0 && ~dir) || (~q2 && ~q1 && ~q0 && ~dir) || (~q3 && ~q0 && dir) || (~q2 && ~q1 && ~q0 && dir)), .clk(clk), .clrn(rst), .q(q0));

DFF A2(.d((~q3 && q2 && ~q1 && ~q0 && ~dir) || (q3 && ~q2 && ~q1 && ~q0 && ~dir) || (~q3 && q1 && q0 && ~dir) || (~q3 && ~q1 && q0 && dir ) || (~q3 && q1 && ~q0 && dir)), .clrn(rst), .clk(clk), .q(q1));

DFF A3(.d(( q3 && ~q2 && ~q1 && ~q0 && ~dir) || (~q3 && q2 && q0 && ~dir) || (~q3 && q2 && q1 && ~dir) || (~q3 && ~q2 && q1 && q0 && dir) || (~q3 && q2 && ~q1 && dir) || (~q3 && q2 && ~q0 && dir)), .clrn(rst), .clk(clk), .q(q2));

//msb

DFF A4(.d((~q3 && ~q2 && ~q1 && ~q0 && ~dir) || (q3 && ~q2 && ~q1 && q0 && ~dir) || (q3 && ~q2 && ~q1 && ~q0 && dir) || (~q3 && q2 && q1 && q0 && dir)), .clrn(rst), .clk(clk), .q(q3));

If I program the Cyclone with these code everything works fine. So it count from 0..9 (dir = 1) and from 9..0 (dir = 0). But the problem occurs when I use the Cyclone II device. It count first from 0..9 but after the first overflow, it counts only 0,3,6,9,0,... and so on. So the problem must be the Quartus software, because the source code is the same, the clock frequency is the same and all cofigure procedures are correct. Only the device and the pinning for the IO's are different.

So were is the problem??