Altera_Forum
Honored Contributor
15 years agoIllegal Time Range for Launch/Latch Clock Relationship
In using TimeQuest, I have come across the following warning:
"Warning: The launch and latch times for the relationship between source clock: V_AABCLK1 and destination clock: bpll|altpll_component|auto_generated|pll1|clk[0] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0." In this particular case, the source clock is 3.072MHz and the destination clock is 54MHz. In my design, I passed the corresponding data signal through a synchronizing chain in which I registered the signal first at 3.072MHz and then twice at 54MHz. I am seeing negative setup slack related to the crossover between the 3.072MHz register and the first 54MHz register. I have come across one other post with relation to this error and absolutely nothing in terms of the Altera documents. Any assistance in understanding what is creating this warning would be greatly appreciated.