New ContributorIgnoring clock skews in set_max_delay constraint
Hi
I have a clock domain crossing in my design and I have placed synchronisers at the crossing paths. I have specified the constraint set_max_delay -from [src clk] -to [dest_clk] [time period of src clk] for avoiding timing errors on the crossing paths.
However Quartus is throwing timing errors with huge clock skews between the 2 clocks. I wanted to know how we can specify to ignore the clock path skews in such a scenario.
I have seen related discussions (https://community.intel.com/t5/Programmable-Devices/set-max-delay-vs-set-net-delay/td-p/232670) but couldn't understand any solution out of it.
I am using Arria 10 FPGA and Quartus 19.3 Prime Pro Version.
Without looking at your design, if these clock domains are asynchronous, you should use set_clock_groups to simply cut all paths between them. By using set_max[min]_delay, the tool will still analyze timing on paths that go between these clock domains and you see what's happening.
So simply try this instead of set_max[min]_delay:
set_clock_groups -asynchronous -group src_clock -group dest_clk
If the clock domains are synchronous to each other and you're still getting timing failures, then you may need to look into using multicycles or, better yet, adding registers or using a FIFO to handle the clock crossings.
#iwork4intel
