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VHDL. It's always about the type. :)

It seems strange that your buttons b0 and b1 are being compared against 4-bits, "0000". I would have assumed they were standard_logic and not vectors, and you would just compare against '0'. Similarly, seems strange that your counters are single bits. FYI, and others will disagree, but I've always avoided variables when writing VHDL. There are times they come in really handy, but 95% of the time I see them you can write the same thing without a variable.

(I don't like variables because they don't correlate directly to anything in hardware, where signals seem much more like drawing a schematic. I feel like you have better control and less likely to have strange stuff occur. This is purely a matter of preference, as I once worked with someone much smarter than me, who did everything with variables, and knew exactly what he was doing. The only drawback I would says is most people who looked at his code didn't understand what he was doing...)

I agree with rysc - no variables. Theres nothing you can do with a variable that you cant do with a signal (and signals make more sense for logic).

You also shouldnt have counters in unclocked processes (because they wont actually count).