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Does it mean that it is not possible with the Modelsim starter to simulate the design that uses the predefined functions in Megarfunction?
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The MegaFunctions come with simulation models. Lots of the lower-level components have both Verilog and VHDL support. However, components such as the Avalon-MM bus BFMs and other SOPC/Qsys components are only available in Verilog.
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Starter only supports single-language compilation, does this mean without a license, we can only simulate the pure HDL-based designs?
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All designs are pure HDL. The MegaFunctions have HDL simulation models.
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Regarding to HDL language, both Verilog and VHDL are new for me, which do you recommend me to learn for working with Stratix IV GT?
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Learn SystemVerilog. Verilog is a subset of that language.
Cheers,
Dave
Honored Contributor
