If Quartus II Supscription Edition is necessary for desiging with Stratix IV GT

--- Quote Start ---

You cannot synthesize for Stratix IV devices in the web edition of Quartus.

You should be able to simulate with the Modelsim Altera Starter Edition. However, if any of the IP is generated in Verilog format, then you must write all your simulation code in Verilog (or SystemVerilog) format, as the starter edition only supports single-language compilation.

Cheers,

Dave

--- Quote End ---

Thank you very much for your reply and explanation. Does it mean that it is not possible with the Modelsim starter to simulate the design that uses the predefined functions in Megarfunction? Starter only supports single-language compilation, does this mean without a license, we can only simulate the pure HDL-based designs?

Regarding to HDL language, both Verilog and VHDL are new for me, which do you recommend me to learn for working with Stratix IV GT?

Thank you again.