Forum Discussion
Altera_Forum
Honored Contributor
14 years agoYou cannot synthesize for Stratix IV devices in the web edition of Quartus.
You should be able to simulate with the Modelsim Altera Starter Edition. However, if any of the IP is generated in Verilog format, then you must write all your simulation code in Verilog (or SystemVerilog) format, as the starter edition only supports single-language compilation. Cheers, Dave