Forum Discussion
I agree the RLC per pin would be included if the option was selected (I didn't always get that from my FPGA design team). And from what I can tell, the Model Selector would include ODT vs driver for the DQ signals of a DDRx design. But I don't think the tool would allow you to specify a number of different driver models for each signal group (address/control, DQ, clock). At least the wiki post doesn't mention how you would provide a list of such drivers. I generally want to try out the 34 ohm vs 40 ohm driver, for instance, and slew rate selection is always something I am interested in if it is provided (The Stratix 10 did not offer slew rate control for SSTL12 drivers).
So I build an IBIS model with a selection of driver options that I audition as soon as I have a routed PCB to work with. That lets me identify any stubs (in a discrete design) that need to be minimized. You could do that work up front and communicate constraints to the PCB team if your flow allows for that.
So I have Model Selector sections for all three groups of signals. Yes, the tool may not allow selecting a driver that is in the IBIS model and we've worked around that in the past.
I'm curious to know if you have looked at the Agilex IBIS model. I have a separate post on its unique rising/falling waveforms and the huge difference in its slew rate settings. You may have already tripped across the post - it's simply titled "Agilex IBIS Model".