IBIS Model Creation for Agilex Discontinued?

The truth is in order to simulate a DDR4 interface you would need to generate a custom IBIS model anyway. The project specific IBIS would have driver settings that the FPGA designer had chosen, and would lack the 'Model Selector' section that would let you choose from a list of drivers. And without that section, you also can't turn ODT on and off, so you can only simulate in the 'write' direction for data signals.

I have generated my own IBIS model for simulating a DDRx channel for years using a Perl script after realizing it was simply too difficult to build one by using a text editor and copying/pasting the various models. The inputs are a netlist from the schematic, the raw IBIS model for the FPGA family, and (very important) the RLC for the package. Intel provides the IBIS model on their site but requires you to request the package RLC using a support ticket. And no, the RLC on the download site will not work - it is a default (likely an average) for any pins that don't have RLC values, and you have to have pin-specific RLC in your IBIS model if order to do any serious simulations (gives impedance and flight time info). The RLC should match the length information for the package so your PCB designer can match lengths to the DRAMs.

I simply include a short list of drivers in the custom IBIS model that I am likely to want to 'audition' and leave the rest of the models out - in the past IBIS models grew to over 300MB which made them very slow to access by the simulator. And each type of signal (DQ, Clock, Address/Control) gets a list of valid drivers to choose from (DQ get POD drivers, etc) in the Model Selector section.

So the project IBIS was partly helpful, but still needed alot of work to make it useful for simulation - creating one from scratch is really the only way to have an IBIS model that is useful in simulations. Hope this is helpful.