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Altera_Forum
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11 years ago

I2C Protocol help

Hi, I am new to VHDL. I am trying to implement an I2C master for practice (synthesizable code). At the moment , I have code written to send the start bit and then 8 data bits. The SDA should chan...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Realistically, a typical FPGA system clock frequency (crystal or PLL generated clock) will be rather 20 or 50 MHz than 200 kHz. Respectively, the bit level state machine won't advance every clock cycle but every Nth cycle after expiration of a delay counter.