I2C inout simulation

Hi,

• assigning '0' and 'Z' for 0 and 1 is correct, go on with that

• keep in mind that a real I2C bus has pull-ups, so probably your master has difficulties to detect 'Z' as a logic 1

• you can model pull-ups by assigning 'H' to both signals (SDA and SCL) in your test-bench ('H' is a weak logic 1 driver; this will make sure your signal will go to 'H' when all drivers are 'Z'); this trick of course only works if your signals are std_logic, not with std_ulogic

• don't put the pull-ups in your synthesis code, it's only supposed to be in the testbench!

• in both devices (master and slave) detect a logic 1 by using the statement "if(signal = '1' or signal='H')", instead of just saying "if(signal = '1')"; this will make sure you detect a logic 1 regardless of how you drive it

• note that this works both for simulation and for synthesis (the synthesized design can only distinguish 0 and 1 anyway)