Forum Discussion
AUden
New Contributor
New ContributorI2C implementation in VHDL
Hey ! i am trying to implement i2c protocol using VHDL Language. In my Case Master is Arria V FPGA & Slave is ADV7182. The issue what i am getting is Acknowledgement. I am getting not Acknowledgem...
AUdenNew Contributor
New ContributorI checked on CRO data what i am writing was correct but in acknowlegement clock cycle SDA was high
it should be low in acknowledgement clock cycle.
Well once it get the acknowledgement it should go to state 6 but it was going to ideal state i.e. state 0
So No acknowlegment.
