I want to know the Type declaration and signal declaration.

but i still confused about this part......

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.all;

USE IEEE.STD_LOGIC_ARITH.all;

USE IEEE.STD_LOGIC_UNSIGNED.all;

-- This code displays time in the DE2's LCD Display

-- Key2 resets time

ENTITY DE2_CLOCK IS

PORT(reset, clk_50Mhz : IN STD_LOGIC;

LCD_RS, LCD_E, LCD_ON, RESET_LED, SEC_LED : OUT STD_LOGIC;

LCD_RW : BUFFER STD_LOGIC;

DATA_BUS : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));

END DE2_CLOCK;

ARCHITECTURE a OF DE2_CLOCK IS

TYPE STATE_TYPE IS (HOLD, FUNC_SET, DISPLAY_ON, MODE_SET, WRITE_CHAR1,

WRITE_CHAR2,WRITE_CHAR3,WRITE_CHAR4,WRITE_CHAR5,WRITE_CHAR6,WRITE_CHAR7,

WRITE_CHAR8, WRITE_CHAR9, WRITE_CHAR10, RETURN_HOME, TOGGLE_E, RESET1, RESET2,

RESET3, DISPLAY_OFF, DISPLAY_CLEAR);

SIGNAL state, next_command: STATE_TYPE;

SIGNAL DATA_BUS_VALUE: STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL CLK_COUNT_400HZ: STD_LOGIC_VECTOR(19 DOWNTO 0);

SIGNAL CLK_COUNT_10HZ: STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL BCD_SECD0,BCD_SECD1,BCD_MIND0,BCD_MIND1: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL BCD_HRD0,BCD_HRD1,BCD_TSEC: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL CLK_400HZ, CLK_10HZ : STD_LOGIC;