I use recommend vhdl to instantiate alter ram. How can I add the sclr control to the code?

Hi Xin,

1. The code provided over here, having multiple errors,please provide code which has been compiled without error if possible provide project file(.qar)(Project menu-> Archive Project)

2. true dual port dual clock ram. From ip editor, it only supports two read/write ports with input/output clock, which means all input signal are registered by clock0, and all output signals are registered by clock1. In this case, my understanding is that all signals except q_a and q_b are using clock0, is that correct? -- --here output clock will control only the data output registers & rest of the registers are controlled by input clock.

3. We need to use a two port ram with independent clocks: port A is driven by clock0, ad port B is driven by clock1. --- You have to use Read/Write Clock Mode.

4. Is there any limitation to use true dual ports with independent clocks? --- Yes,this can be done using Emulate TDP dual clock mode & this option is available only if you select With two read/write ports and Customize clocks for A and B ports clocking method.

Refer the below user guide for more details,

https://www.intel.com/content/www/us/en/programmable/documentation/vgo1439451000304.html#pvv1499416508039

Regards,

Vicky