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XCui0's avatar
XCui0
Icon for New Contributor rankNew Contributor
6 years ago

I use recommend vhdl to instantiate alter ram. How can I add the sclr control to the code?

I include the sclr control in my code, but it will not connect to the sclr pin of altera_syncram. I tried to instantiate a ram ip, and enable the sclr, I can see that my sclr will connect to the sclr...
Vicky1's avatar
Vicky1
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Xin,

1. The code provided over here, having multiple errors,please provide code which has been compiled without error if possible provide project file(.qar)(Project menu-> Archive Project)

2. true dual port dual clock ram. From ip editor, it only supports two read/write ports with input/output clock, which means all input signal are registered by clock0, and all output signals are registered by clock1. In this case, my understanding is that all signals except q_a and q_b are using clock0, is that correct? -- --here output clock will control only the data output registers & rest of the registers are controlled by input clock.

3. We need to use a two port ram with independent clocks: port A is driven by clock0, ad port B is driven by clock1. --- You have to use Read/Write Clock Mode.

4. Is there any limitation to use true dual ports with independent clocks? --- Yes,this can be done using Emulate TDP dual clock mode & this option is available only if you select With two read/write ports and Customize clocks for A and B ports clocking method.

Refer the below user guide for more details,

https://www.intel.com/content/www/us/en/programmable/documentation/vgo1439451000304.html#pvv1499416508039

Regards,

Vicky

  • XCui0's avatar
    XCui0
    Icon for New Contributor rankNew Contributor
    6 years ago
    Hi Vicky, Thank you very much for your reply. Attached is my archived project. My question is how I could add the synchronous reset to the code. As you can see, I have a “srst”, but it does not shown on the RTL. For the case of “REL_SP_SC”, “SMP_DP_SC”, “SMP_DP_DC”, all of them can be implemented with RAM block, but no “srst”. The other question is about the implementation of true dual port dual clock RAM, which is the case of “TRU_DP_DC” in my code. I try to implement true dual port RAM different “input/output” clock, as in my code. I give the same clock for writing for both ports, and same clock for reading for both ports. But it fails to instantiate a RAM block, but with logic cells. If I try to implement a true dual port RAM with independent clock for each port, I.e., clk_a for port A read and write, clk_b for port B read and write, Quartus cannot synthesis my code at all. Here, I copied the template from Quartus for true dual port dual clock -- Port A process(clk_a) begin if(rising_edge(clk_a)) then if(we_a = '1') then ram(addr_a) := data_a; end if; q_a <= ram(addr_a); end if; end process; -- Port B process(clk_b) begin if(rising_edge(clk_b)) then if(we_b = '1') then ram(addr_b) := data_b; end if; q_b <= ram(addr_b); end if; end process; Is the above code to implement a Emulate TDP? How could I add “srst” control to it? Thanks a lot! Xin Sent from Mail<https://go.microsoft.com/fwlink/?LinkId=550986> for Windows 10
  • XCui0's avatar
    XCui0
    Icon for New Contributor rankNew Contributor
    6 years ago
    Hi Vicky, It seems like the following code I copied from Quartus template is not supported for stratix 10. If I want to use Emulate TDP, is it possible instantiate by using VHDL code? Or I have to use the IP editor? Thank you very much! Xin Sent from Mail<https://go.microsoft.com/fwlink/?LinkId=550986> for Windows 10