I only get the last 64 data when I using master read

I refer to Avalon MM templates to write a code for master read

But I only get the last 64 data when I using master read

For example : I want to my output are 0~127 , but I only get 65~127

is some signals I forgot to setup ?

thanks

`timescale 1ns/1ns
module master (
 clk,
 reset,
    master_address,
    master_byteenable,
master_waitrequest,
            go,
/////////////////write///////////////////////
        master_write,
    master_writedata,
    source_data,
 write_addr,
   write_en,
///////////////////////////////////////////////////////////////////
    master_readdata,
        master_readdatavalid,
        to_addr_readdata,
     read_en,
     read_addr,
        master_read,
        index,
//      for_read_en
        fifo_ren,
        fifo_wen,
        fifo_clk,
        for_fifo
        );
input                clk;
input                reset;
input  index;
output  fifo_wen;
output  reg fifo_ren;
output fifo_clk;
// DDR2 master port
input for_fifo;
output    reg        master_address;
output            master_byteenable;
input                master_waitrequest;
output                 go;
input               write_en;
/////////////////write///////////////////////
output                master_write;
output            master_writedata,to_addr_readdata;
input            source_data;
input           write_addr;
///////////////////////////////////////////////////////////////////
input            master_readdata;
input        master_readdatavalid;
output    reg    master_read;
input               read_en;    
input  read_addr;    
//////////////////////////////////////////////////////////
reg  to_addr_readdata;
wire read_go,write_go;
 assign master_byteenable = -1;  
 
assign master_writedata = source_data;
 assign go = master_waitrequest;
assign fifo_clk_1 = (  clk & (!master_waitrequest) & for_fifo);
assign fifo_clk = (fifo_clk_1  & master_read);
assign fifo_wen = (read_en && (!master_waitrequest));
always @(posedge clk or negedge reset)
 
     begin
        if (!reset)
        begin
          to_addr_readdata <=# 1 0;
          master_address <=# 1 0;
          master_read <=# 1 0;
        end     
     
     else
        begin
          to_addr_readdata <=# 1 master_readdata;
          master_address <=# 1 read_addr;
          master_read <=# 1 read_en;
        end
    end
endmodule