Forum Discussion
Altera_Forum
Honored Contributor
13 years agoThe simulator does not know what you want for the initial value for Q. Supply an initial value for the signal, eg.,
-- Difining signal(s)
signal Q : std_logic_vector(25 downto 0) := (others => '0');
and it will work fine. An alternative method is to add a reset input and then add reset logic to the counter process. Cheers, Dave