I having problem with University Program VWF.

Hello,

The problem with your code appears to be that you are not setting the output data_out otherwise; instead, you are only assigning a value to it when the r_enable input is high. The output data_out will thus keep its prior value, which in this case is uninitialized, resulting in 0000 output when the r_enable input is low.

The current value of registerIS can be assigned to data_out when r_enable is low by adding an else statement to your always block to address this problem. This will guarantee that, even when r_enable is low, data_out always represents the current value of registerIS.

Changes:

module register (clock, r_enable, w_enable, data_in, data_out);

input clock;

input r_enable;

input w_enable;

input [3:0] data_in;

reg [3:0] registerIS;

output reg [3:0] data_out;

always @(posedge clock) begin

if (w_enable) begin

registerIS <= data_in;

end

else if (r_enable) begin

data_out <= registerIS;

end

else begin

data_out <= data_out;

end

end

endmodule