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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

i have question about verilog. i coudln't make one clock. will u help me please.

i attached file & picure. our team creating uart verilog code. by using modelsim. i have 4 modules for FPGA and one module for simulation as like testbench. so i will explain shortly....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thank you for your help. I appreciate. Haha thanks! I was not good yesterday about feeling but right now I feel happy ! Thanks again. Sleep well !! Good night