I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Hi KhaiY, the vhdl file contains a component named BRAM_16x1S as part of the archive BRAM16x2 archtecture. It works splendidly as it is in Xilinx ISE 14.6. But Quartus 13.x fails to compile this same vhdl file. This is that file:

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 22:57:22 05/09/2020

-- Design Name:

-- Module Name: BRAM_16x2 - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

--BRAM_16x2 blz.194

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity BRAM_16x2 is

port (q_out : out std_logic_vector (1 downto 0);

write_en : in std_logic;

clk: in std_logic;

d_in: in std_logic_vector (1 downto 0);

a_in: in std_logic_vector (3 downto 0));

end BRAM_16x2;

architecture BRAM_arch of BRAM_16x2 is

component BRAM_16x1S is

port(O : out std_logic;

D: in std_logic;

A3, A2, A1, A0: in std_logic;

WE, W_CLK: in std_logic);

end component;

begin

U0: BRAM_16x1S port map (O =>q_out(0), WE =>write_en, W_CLK =>clk, D =>d_in(0),

A0 =>a_in(0), A1 =>a_in(1), A2 =>a_in(2), A3 =>a_in(3));

U1: BRAM_16x1S port map (O =>q_out(1), WE => write_en, W_CLK => clk, D =>d_in(1),

A0 =>a_in(0), A1 =>a_in(1), A2 =>a_in(2), A3 =>a_in(3));

end BRAM_arch;

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I'll add it hereby as attachement too.

Thanks again for taking the time to look into the problem!

Albert.