Hyper-Retiming, How to disable it in the .qsf?

Hi Alex,

I've tried an example ASIC Prototyping project targeting Stratix 10 GX 10M and found the same observations as you. I have reported this issue to our engineering team. Below are my findings when using ASIC_PROTOTYPING_FEATURES:

1. After running fitter, I can see that there is a drop in runtime spent at retimer, however it's not completely skipped (I think this is an expected behaviour, need engineering team to confirm)
2. Received below info messages indicating the tool is trying to retime the project. But when I check the retiming limit details report, it says that meeting requirements for all clock domains are met and therefore does not require any optimization. This is obviously a bug, engineering team is currently investigating the problem.

Info(17966): Starting Hyper-Retimer operations.

Info(18914): The Hyper-Retimer was unable to optimize the design due to retiming restrictions. Run Fast Forward Timing Closure Recommendations to see step-by-step suggestions for design changes and show the estimated performance improvement from making these changes.

Info(17968): Completed Hyper-Retimer operations.

I'll let you know what the engineering team comes back with.

In the meantime, to reduce compile time you may try using "Aggressive Compile Time" Optimization Mode. To set this, go to Assignments>Settings>Compiler Settings>Optimization Mode. This would reduce the general compilation time hence reduce performance. Based on our findings the retime stage will not be skipped entirely but this optimization mode should reduce the whole compilation.

More info here: https://www.intel.com/content/www/us/en/docs/programmable/683236/21-3/optimization-modes.html

Regards,

Nurina