Huge interconnect delays on Arria10 input paths

I would like to add one really interesting additional observation:

When we set

set_instance_assignment -name VIRTUAL_PIN ON -to <all_io_with_timing_trouble>

then we would have expected the timing issues to go away. But the timing issues persist. Please refer to the following images showing the timing analysis and chip planner screenshots of the now internal paths which formerly were input paths:

As can be seen, the huge delays are still present, but now on ridiculously short internal paths. This now really does not make sense.

Is there anything we could try to find out why the timing analyzier and chip planner think that this path has such a huge delay?

Again, thanks a lot in advance for any insight you could provide!

Florian