Forum Discussion
I am going to use HPS_GPIO,64,65,66 pins from Cyclone V formware. Just to use in code without Quartus as I understand is not possible. I have to initialize these HPS GPIOs in Quartus. I try to do this:
module DE10_NANO_SPI(
......
inout HPS_GPIO64,
inout HPS_GPIO65,
inout HPS_GPIO66
);
hps u0 (
........
.hps_io_hps_io_gpio_inst_GPIO64 (HPS_GPIO64), // .hps_io_gpio_inst_GPIO64
.hps_io_hps_io_gpio_inst_GPIO65 (HPS_GPIO65), // .hps_io_gpio_inst_GPIO65
.hps_io_hps_io_gpio_inst_GPIO66 (HPS_GPIO66) // .hps_io_gpio_inst_GPIO66
);
And during Partition Merge have got next warnings and errors. Please, suggest what is not correct.
Critical Warning (35033): Found I/O pins in lower-level partitions that are not connected in the top-level design
Critical Warning (35034): I/O cell "hps:u0|hps_hps_0:hps_0|hps_hps_0_hps_io:hps_io|hps_hps_0_hps_io_border:border|hps_io_gpio_inst_GPIO64[0]~output" is not connected to partition "hps_hps_0_hps_io_border:border"
Critical Warning (35034): I/O cell "hps:u0|hps_hps_0:hps_0|hps_hps_0_hps_io:hps_io|hps_hps_0_hps_io_border:border|hps_io_gpio_inst_GPIO65[0]~output" is not connected to partition "hps_hps_0_hps_io_border:border"
Critical Warning (35034): I/O cell "hps:u0|hps_hps_0:hps_0|hps_hps_0_hps_io:hps_io|hps_hps_0_hps_io_border:border|hps_io_gpio_inst_GPIO66[0]~output" is not connected to partition "hps_hps_0_hps_io_border:border"
Error (35030): Partition "hps_hps_0_hps_io_border:border" contains I/O cells that do not connect to top-level pins or have illegal connectivity
Error (13176): Port: I_GPIO2_PORTA_I of HPS atom "hps:u0|hps_hps_0:hps_0|hps_hps_0_hps_io:hps_io|hps_hps_0_hps_io_border:border|hps_io_gpio_inst_GPIO64[0]~output" must be connected to a top-level pin
Error (13176): Port: I_GPIO2_PORTA_I of HPS atom "hps:u0|hps_hps_0:hps_0|hps_hps_0_hps_io:hps_io|hps_hps_0_hps_io_border:border|hps_io_gpio_inst_GPIO65[0]~output" must be connected to a top-level pin
Error (13176): Port: I_GPIO2_PORTA_I of HPS atom "hps:u0|hps_hps_0:hps_0|hps_hps_0_hps_io:hps_io|hps_hps_0_hps_io_border:border|hps_io_gpio_inst_GPIO66[0]~output" must be connected to a top-level pin
In Platform Designer my HPS GPIOs looks like:
I am going to use them as outs, writting 0 or 1 to their DR register, DDR register contains 1 - configured as out