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emery's avatar
emery
Icon for New Contributor rankNew Contributor
4 years ago
Solved

HPS Peripheral FPGA Clocks parameters

Cyclone V Hard Processor System Technical Reference Manual 2021.07.08 states “If I2C 2 peripheral is routed to FPGA, use the input field to specify I2C 2 output clock frequency” In Quartus Platf...
  • emery's avatar
    emery
    4 years ago

    Thanks @aikeu


    It sounds like you are saying that when Technical Reference Manual 2021.07.08 states on page 27-11 “If I2C 2 peripheral is routed to FPGA, use the input field to specify I2C 2 output clock frequency” it is meaning this field sets an input clock source frequency and not the output frequency on SCL.

    And that this input frequency is divided down by a value in register ic_con to get SCL frequency.

    Reading further in Technical Reference Manual I do see that it says "The I2C controller can operate in standard mode (with data rates of up to 100 Kbps) or fast mode (with data rates less than or equal to 400 Kbps)."

aikeu's avatar
aikeu
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi emery,


You can you can set the operating SCL output through the register ic_con, referring to the Cyclone V technical reference manual. The input clock source will be divided accordingly.


Thanks.

Regards,

Aik Eu


emery's avatar
emery
Icon for New Contributor rankNew Contributor
4 years ago

Thanks @aikeu


It sounds like you are saying that when Technical Reference Manual 2021.07.08 states on page 27-11 “If I2C 2 peripheral is routed to FPGA, use the input field to specify I2C 2 output clock frequency” it is meaning this field sets an input clock source frequency and not the output frequency on SCL.

And that this input frequency is divided down by a value in register ic_con to get SCL frequency.

Reading further in Technical Reference Manual I do see that it says "The I2C controller can operate in standard mode (with data rates of up to 100 Kbps) or fast mode (with data rates less than or equal to 400 Kbps)."