HPC II DDR controller performance

I have the controller integrated and working and now just trying to optimize performance.

Using HPC II, Full "Controller data rate" with half rate bridge.

The read/write behavior is write data to consecutive addresses (~200 writes)

followed by read data from consecutive addresses (~200 reads).

And continuing to alternate between write and read sequences indefinitely.

For some sequences, the writes are interrupted say half way through by

almost 30 local clock cycles of mast_ready = '0' thus holding off

further writes.

For some write sequences, 200 writes can go through without interruption.

I am trying to understand what specifically causes this and looking for ways

to minimize the number of pause cycles(due to mast_ready='0').

More specific numbers....

From start of write sequence to end is 205 cycles.

Paused cycles (due to mast_ready='0') are 34 (occurs in 3 groups of 4, 10, 20 cyc).

This gives me 83.4% efficiency. And I am looking for more.

For now, I really only need maybe 10 minimum of these pause cycles removed

for eff = 88.3 % to meet system requirements but high as possible is naturally better.

Using Quartus 9.1. Custom hardware.

Possibly some of the configuration options for the controller could be adjusted?

The memory preset settings could be a little off from the datasheet but would this

be relevant - trying to understand what "buttons to push" to improve things.

Thanks all,

Cos.