HPC II DDR controller performance

Still no comments...

I myself put the "memory preset settings" as per the memory datasheet.

Rebuilt and saw no noticeable difference. They were not that far off.

I myself made an adjustment to the controller config which was just changing the

look ahead queue depth to 8 (was 4).

Rebuilt and saw no noticeable difference.

My local logic is not using bursts but not sure that that matters in this case.

The mast_write is always high(cycle to cycle) unless mast_ready goes low.

Again, no issues in some sequences of ~200 writes.

Still trying to understand the root cause of mast_ready being low for

so many cycles. If I knew that then I could target a change towards that.

Would bursts make a difference? HPC II controller is somewhat of a black box.

It would be good for me to understand what kind of performance

I should be seeing.

Hope to see some replies on this.

Thx,

-Cos