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Altera_Forum
Honored Contributor
18 years agoI tried so and still get an error with Modelsim: "IndexValue 32768 is out of range (32767 ... 0)" just as with the former file.
I also cutted my ram into 4 peaces to partially load them. I currently have 4 rams like this here : ENTITY dpram_16_32_1 IS PORT ( clock : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); rdaddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0); wraddress : IN STD_LOGIC_VECTOR (13 DOWNTO 0); wren : IN STD_LOGIC := '1'; q : OUT STD_LOGIC_VECTOR (63 DOWNTO 0) ); END dpram_16_32_1; ... and applied to each of them a individual hex like this here : :04000000F4E4000024 :04000400E9C8F4E46F :04000800E9C8F4E46B :04000C00E9C8F4E467 :04001000E9C8F4E463 :04001400F4E4E9C85F ...... Modelsim (AE+SE) still refuses to work with it, while synthesis runs to the end. What appears strange to me: It does no matter to which of the two Ports the HEX file is assigned to in the wizzard. Synthesis works in both cases. I checked the sources of the dpram.vhd and found , that the assignment worked: In one case PORTA was assigned and in the other case PORTB. ?