How would you debug an issue that goes away when SignalTap is added?

Occasional errors are ususally related to timing issues, particularly incorrect processing of asynchronous signals. Hearing about a problem that occurs at system boot let me think either of a problem with asynchronous released reset or with the relation of PLL startup and reset of modules driven by generated clocks.

If the problem is known to occur only at startup, it may be easier to add safe state machine logic to the affected modules (if they are regular state machines) or similar user coded means that recover from deadlock.

SignalTap always changes the routing of a design. To debug the original design, gate level analysis with Modelsim can help. It will indicate those logic operations, where the design timing makes the result potentially unpredictable. You are also able to vary the timing of external signal systematically in the testbench.