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Altera_Forum's avatar
Altera_Forum
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16 years ago

How use sram?

I must use the sram on fpga Cyclone ii with quartus ii.

How can i use it?

I have used the megafunction but i don't see in the istantion the chip enable, read enable and other signals.

Is there a component in a specific library for the use of sram?

Thank you!

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    baghiero83:

    --- Quote Start ---

    I must use the sram on fpga Cyclone ii with quartus ii.

    How can i use it?

    I have used the megafunction but i don't see in the istantion the chip enable, read enable and other signals.

    --- Quote End ---

    I suppose you are trying to use the Cyclone II on-chip memory.

    The MegaWizard is an efficient tool to generate a specific RAM for you. The RAM block at least has both an input port AND an output port. You only need a signal wren for writing. Reading is always done on every clock cycle.

    The signals you are refering to are signals that occur when you are sharing the input- and output lines of your RAM. By making a wrapper arround the MegaWizard RAM block you can constrain yourself to only using one port for both reading and writing that you can then interface via an external tri-state bus. Internally on the FPGA I do not see the usage of this.
  • Altera_Forum's avatar
    Altera_Forum
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    Thanks, so i can't use the chip enable because the ram is always enabled?

    Are you sure that when i use megawizard ram , i use sram and not sdram on-chip?

    How can i constraint myself to using one port?

    Thank you very very much!
  • Altera_Forum's avatar
    Altera_Forum
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    baghiero83:

    --- Quote Start ---

    Thanks, so i can't use the chip enable because the ram is always enabled?

    --- Quote End ---

    The Ram is always enabled. If you want a chip enable, you have to add it yourself.

    --- Quote Start ---

    Are you sure that when i use megawizard ram , i use sram and not sdram on-chip?

    --- Quote End ---

    On a normal CMOS chip you normally only have SRAM blocks. The Block RAMs on FPGAs are SRAM. DRAM requires a special technology that is not compatible with normal CMOS technology. So there are no DRAMs on FPGAs up to now. DRAMs are separate chips.

    --- Quote Start ---

    How can i constraint myself to using one port?

    --- Quote End ---

    I do not understand why you would like to do this on-chip of the FPGA?

    1) Do you want to access the FPGA on-chip memory from outside?

    2) Do you want to access of-chip memory from your FPGA
  • Altera_Forum's avatar
    Altera_Forum
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    The out bitstream of the sram must be the input of a Flip flop chain

  • Altera_Forum's avatar
    Altera_Forum
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    but i want also read with an oscilloscope the out bitstream of the sram