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DNguy11's avatar
DNguy11
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6 years ago

How to write a Verilog to implement -MULT(27x27) so that QPRO map the full functionality to 1 DSP?

Using QPRO it is possible to build an IP to implement -(X*Y) where X and Y are of 27 bit-width. However I find NO verilog writing style such that QPRO is able to map the full functionnality within 1 ...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

If that is the case, you might have to use the IP from the IP catalog. Can you look into using those?

  • DNguy11's avatar
    DNguy11
    Icon for New Contributor rankNew Contributor
    6 years ago

    For portability reason I need to go though Verilog. Does it mean that QPRO is not able to infers such a basic DSP functionality?